Jian-Cheng Lin received his B.S from National Chung-Cheng University(中正大學) in Taiwan, 2003, and M.S from National Tsing Hua University(清華大學) in Taiwan, 2005. The lab of his graduate school was NTHUCAD Lab(超大型積體電路暨電腦輔助設計實驗室). He joins "Defense Industry Reserve Duty System"(國防工業訓儲役) after the graduate school and went to military training as a Second Lieutenant officer. In this system, he is now working in SpringSoft as an engineer.
In the graduate school, his research fields were logic synthesis, place and routing in VLSI/CAD and EDA area. He did many in these years, such as Flip-chip placement, Watermarking-based Intellectual Property Core Protection Scheme, Spare Cells Selection for Functional Change, and many VLSI Physical Design Automata works.
In the research field, His interested area are logic synthesis, floorplaning and routing, and electronic design automation. Professional abilities are Linux/Windows, Win32 SDK, Microsoft Foundation Class(MFC), Intel 80×86 Assembly Language, C/C++, and PHP. In IC design field, he's capable of writing Verilog HDL, using Synopsys Design Compiler and Astro (Avant! Apollo) Automatic Place and Routing tools. In the mean time, he is contributed to Apple Cocoa & Objective-C projects.